Data and code underlying the research of: SRIF-ADC for CIM accelerators

This targets neuromorphic and general-purpose arithmetic applications. A scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures is presented, suitable for stringent power and area constraints. Techniques to stabilize the node receiving analog in-puts are implemented that allow more rows to be activated at the same time, thereby improving the scalability in terms of higher parallelism of operations. A self-timed variation-aware design approach is introduced along with design measures to drastically reduce the read disturb of memristor devices. In addition, a compact, built-in sample-and-hold circuit to replace the typically used large-sized capacitance is present along with a built-in weighting technique to alleviate the need for post-processing when combining outputs of different bit significance. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.